Flash memory is a commonly used type of non-volatile memory in widespread use as mass storage for consumer electronics, such as digital cameras and portable digital music players for example. The density of a presently available flash memory chip can be up to 32 Gbits (4 GB), which is suitable for use in popular USB flash drives since the size of one flash chip is small.
FIG. 1 is a general block diagram of typical flash memory of the prior art. flash memory 10 includes logic circuitry such as control circuit 12, for controlling various functions of the flash circuits, registers for storing address information, data information and command data information, high voltage circuits for generating the required program and erase voltages, and core memory circuits such as row address decoder 14 and row address decoder buffer 16 for accessing the memory array 18. The control circuit 12 includes a command decoder and logic for executing the internal flash operations, such as read, program and erase functions. The functions of the shown circuit blocks of flash memory 10 are well known in the art. Persons skilled in the art will understand that flash memory 10 shown in FIG. 1 represents one possible flash memory configuration amongst many possible configurations.
The memory cell array 18 of the flash memory 10 of FIG. 1 consists of any number of banks, which is a selected design parameter for a particular flash device. FIG. 2 is a schematic illustration showing the organization of one bank 20 of the memory cell array 18 of FIG. 1. Bank 20 is organized as blocks (Block[0] to Block[k]), and each block consists of pages (WL0 to WLi). Both k and i are non-zero integer values. Each page corresponds to a row of memory cells coupled to a common wordline. A detailed description of the memory cells of the block follows.
Each block consists of NAND memory cell strings, having flash memory cells 22 serially coupled arranged and electrically coupled to each other. Accordingly, wordlines WL0 to WLi are coupled to the gates of each flash memory cell in the memory cell string. A string select device 24 coupled to signal SSL (string select line) selectively connects the memory cell string to a bitline 26, while a ground select device 28 coupled to signal GSL (ground select line) selectively connects the memory cell string to a source line, such as VSS. The string select device 24 and the ground select device 28 are n-channel transistors.
Bitlines 26 (BL0 to BLj, where j is a non-zero integer value) are common to all blocks of bank 20, and each bitline 26 is coupled to one NAND memory cell string in each of blocks [0] to [k]. Each wordline (WL0 to WLi), SSL and GSL signal is coupled to the same corresponding transistor device in each NAND memory cell string in the block. As those skilled in the art should be aware, data stored in the flash memory cells along one wordline is referred to as a page of data.
Coupled to each bitline outside of the bank 20 is a data register 30 for storing one page of write data to be programmed into one page of flash memory cells. Data register 30 also includes sense circuits for sensing data read from one page of flash memory cells. During programming operations, the data registers perform program verify operations to ensure that the data has been properly programmed into the flash memory cells coupled to the selected wordline. To achieve high density, each flash memory cell will store at least two bits of data, and is generally referred to as a multi-bit-cell (MBC).
Those skilled in the art will understand that an issue with MBC flash memory is the sensitivity of its memory cells to program disturb. Program disturb results from the capacitive coupling between adjacent wordlines and floating gates, which are formed closer to each other with each fabrication technology generation. Hence, high voltages applied to one cell during programming can shift a programmed threshold voltage of an adjacent cell to one representing a different logic state, while the programmed state of one cell can affect the threshold voltage of an adjacent cell currently being programmed. To minimize program disturb in MBC flash memory, programming within a block will start at the page corresponding to WL0, and proceed sequentially up to WLi. Alternately, programming can start at WLi and proceed sequentially down to WL0. These schemes for programming NAND MBC flash memory cells are well known in the industry. Once the block has been fully programmed with data, programming of the next file or set of data begins at WL0 of the next block. Within a device, blocks are typically programmed in sequence.
It is well known that flash memory devices have a limited number of erase-program cycles before they can no longer be used to store data reliably. More specifically, flash memory cells are subject to program/erase cycle wearing, which is a progressive degradation of a flash memory cell due to cumulative program and erase operations. Those skilled in the art will understand that a memory block is always erased first prior to being programmed with data, hence the cycles can be referred to as both program and erase cycles. All currently known flash memory is configured for block erase, meaning that if just one page of data in a block is to be modified/updated, the entire block containing that page is erased and re-programmed with the modified page and the unmodified pages. The effect of such cumulative program and erase operations is the alteration of the program and erase characteristics of the memory cell beyond optimal parameters. When memory cells are degraded, higher program and erase voltages are needed to program or erase the memory cells to the desired threshold voltages. Eventually, the memory cells will fail to retain data properly, which is represented as a programmed threshold voltage. For example, the typical erase-program cycles for an MBC flash memory is about 10,000 cycles.
Currently, most flash memory available is of the MBC type due to the large storage density relative to its chip size. While this is suitable for most consumer applications, the 10,000 cycle program-erase limit may be insufficient for other applications where data programming and erasing is frequent. Therefore, when an MBC flash memory has reached its 10,000 cycle life span, it is no longer usable and must be discarded. This problem is more critical for commercial applications, such as HDD applications, where there are more frequent program-erase cycles. Because HDD applications require higher data integrity than most consumer applications, MBC flash memory is not suited for use due to its relatively short 10,000 cycle life span.
This problem is compounded by the fact that the block size of flash memory devices continues to increase while the data file sizes being stored remain relatively static. For example, block sizes for present day high density flash devices are in the range of 256 KB, but future high density flash devices will have block sizes approaching 512 KB. If the data file stored in the block is small, then more memory cells will be unnecessarily subjected to erase/program cycles relative to a block have the size when the data file is modified.
It is, therefore, desirable to provide a flash memory device operable to have an extended life span.